1. Field of the Invention
The present invention relates to techniques for determining the performance of an integrated circuit. More specifically, the present invention relates to a method and apparatus for accounting for the statistical distribution of performance-related parameters while determining the performance of an integrated circuit.
2. Related Art
Static timing analysis (STA) is often used to compare the performance of a circuit against the desired performance metrics. If the desired performance characteristics are not met, the circuit is typically redesigned and STA is rerun. FIG. 1 presents a block diagram illustrating the process of determining the timing for a circuit, which includes flip-flops 101-102, a number of gates, and a clock signal 100, which has a period tP. Launch path 103 is the path from clock signal 100 to the clock input of flip-flop 101, and tL is the time required for a signal to traverse launch path 103. Capture path 104 is the path from clock signal 100 to the clock input of flip-flop 102, and tC is the time required for a signal to traverse capture path 104. Data path 105 is the path from the “Q” output of flip-flop 101 to the “D” input of flip-flop 102, and tD is the time required for a signal to traverse data path 105.
In FIG. 1, the setup and hold slacks are evaluated at flip-flop 102. Flip-flop 102 has a setup time requirement of tSETUP and a hold time requirement of tHOLD. Hence, the setup slack and hold slacks are:setup slack=min(tC+tP)−max(tL+tD+tSETUP)hold slack=min(tL+tD)−max(tC+tHOLD).
While performing STA, variations in the parameters for an integrated circuit (IC) manufacturing process need to be taken into account. One technique to account for such variations is to use bounding techniques while performing STA. FIG. 2 presents a block diagram illustrating the process of calculating the timing for a circuit using such a bounding technique. The circuit in FIG. 2 includes gates 200-202 wherein the worst-case timing of each gate is between 1-2 time units. After a signal passes through gate 200, the signal arrives at the output of gate 200 a minimum of 1 time unit and a maximum of 2 time units after entering gate 200. After the signal passes through gate 201, the signal arrives at the output of gate 201 a minimum of 2 time units and a maximum of 4 time units after entering gate 200. After the signal passes through gate 202, the signal arrives at the output of gate 202 a minimum of 3 time units and a maximum of 6 time units after entering gate 200. Note that the above-described timing analysis technique uses the worst-case timing for each gate, which results in safe timing, but physically improbable.
Unfortunately, increasing clock frequencies are making it more difficult to meet timing constraints. This problem is magnified by the overly-pessimistic worst-case timing analysis techniques used in present STA techniques.
One solution to this problem is to use a statistical technique to calculate the timing for a circuit. FIG. 3 presents a block diagram illustrating the process of calculating the worst-case timing for a circuit using such a statistical technique. The circuit includes gates 300-302 wherein the worst-case timing of each gate is represented as a distribution of possible timings wherein the minimum is 1 time unit and the maximum is 2 time units. After a signal passes through gate 300, the distribution of arrival times for the signal at the output of gate 300 is a minimum of 1 time unit and a maximum of 2 time units after entering gate 300. After the signal passes through gate 301, the distribution of arrival times for the signal at the output of gate 301 is a minimum of 2.45 time units and a maximum of 3.65 time units after entering gate 300. After the signal passes through gate 302, the distribution of arrival times for the signal at the output of gate 302 is a minimum of 3.75 time units and a maximum of 5.25 time units after entering gate 300. Note that this technique provides a more accurate view of the timing of the circuit and is less pessimistic than the bounding technique. Unfortunately, performing statistical STA (SSTA) in this way is computationally costly because operations performed on variation probability distributions are resource-intensive. Furthermore, if the variations are correlated to one another, finding an acceptable solution becomes even more complex and time consuming. Note that correlated variation distribution functions are distribution functions that are statistically dependent, whereas uncorrelated variation distribution functions are statistically independent.
Hence, what is needed is a method and an apparatus for determining the performance of an IC without the problems described above.